Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept

Armin Tajalli, Eric Vittoz, Yusuf Leblebici, Elizabeth J. Brauer

Research output: Chapter in Book/Report/Conference proceedingConference contribution

21 Citations (Scopus)

Abstract

This article presents a novel and robust approach for implementing ultra-low power MOS current mode logic (MCML) circuits. To operate at very low bias currents, a simple and compact high resistance load device has been introduced. Operating in subthreshold regime, the circuit can be used in a very wide frequency range by adjusting the bias current without any need for resizing the devices. Measurements in 0.18 μm CMOS technology show that the proposed MCML circuit can be operated reliably with bias currents as low as 1 nA offering a significant improvement of the power-delay product compared to conventional CMOS gates. Simulations show that the proposed circuit exhibits faster response compared to the conventional MCML circuits with triode-mode PMOS load devices at low bias currents.

Original languageEnglish (US)
Title of host publicationESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference
Pages304-307
Number of pages4
DOIs
StatePublished - 2007
EventESSCIRC 2007 - 33rd European Solid-State Circuits Conference - Munich, Germany
Duration: Sep 11 2007Sep 13 2007

Other

OtherESSCIRC 2007 - 33rd European Solid-State Circuits Conference
CountryGermany
CityMunich
Period9/11/079/13/07

Fingerprint

Bias currents
Logic circuits
Triodes
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Tajalli, A., Vittoz, E., Leblebici, Y., & Brauer, E. J. (2007). Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept. In ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference (pp. 304-307). [4430304] https://doi.org/10.1109/ESSCIRC.2007.4430304

Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept. / Tajalli, Armin; Vittoz, Eric; Leblebici, Yusuf; Brauer, Elizabeth J.

ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference. 2007. p. 304-307 4430304.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Tajalli, A, Vittoz, E, Leblebici, Y & Brauer, EJ 2007, Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept. in ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference., 4430304, pp. 304-307, ESSCIRC 2007 - 33rd European Solid-State Circuits Conference, Munich, Germany, 9/11/07. https://doi.org/10.1109/ESSCIRC.2007.4430304
Tajalli A, Vittoz E, Leblebici Y, Brauer EJ. Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept. In ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference. 2007. p. 304-307. 4430304 https://doi.org/10.1109/ESSCIRC.2007.4430304
Tajalli, Armin ; Vittoz, Eric ; Leblebici, Yusuf ; Brauer, Elizabeth J. / Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept. ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference. 2007. pp. 304-307
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