Ultra-low power subthreshold current-mode logic utilising PMOS load device

A. Tajalli, E. Vittoz, Y. Leblebici, E. J. Brauer

Research output: Contribution to journalArticle

17 Scopus citations

Abstract

A novel approach for implementing MOS current-mode logic circuits that can operate with ultra-low bias currents is introduced. Measurements of test structures fabricated in 0.18m CMOS technology show that the proposed PMOS load device concept can be utilised successfully for bias currents as low as 1nA, achieving sufficiently high gain (>3) over a wide frequency range.

Original languageEnglish (US)
Pages (from-to)911-913
Number of pages3
JournalElectronics Letters
Volume43
Issue number17
DOIs
StatePublished - 2007

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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