Ultra-low power subthreshold current-mode logic utilising PMOS load device

A. Tajalli, E. Vittoz, Y. Leblebici, Elizabeth Brauer

Research output: Contribution to journalArticle

16 Citations (Scopus)

Abstract

A novel approach for implementing MOS current-mode logic circuits that can operate with ultra-low bias currents is introduced. Measurements of test structures fabricated in 0.18m CMOS technology show that the proposed PMOS load device concept can be utilised successfully for bias currents as low as 1nA, achieving sufficiently high gain (>3) over a wide frequency range.

Original languageEnglish (US)
Pages (from-to)911-913
Number of pages3
JournalElectronics Letters
Volume43
Issue number17
DOIs
StatePublished - 2007

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Bias currents
Logic circuits

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Ultra-low power subthreshold current-mode logic utilising PMOS load device. / Tajalli, A.; Vittoz, E.; Leblebici, Y.; Brauer, Elizabeth.

In: Electronics Letters, Vol. 43, No. 17, 2007, p. 911-913.

Research output: Contribution to journalArticle

Tajalli, A. ; Vittoz, E. ; Leblebici, Y. ; Brauer, Elizabeth. / Ultra-low power subthreshold current-mode logic utilising PMOS load device. In: Electronics Letters. 2007 ; Vol. 43, No. 17. pp. 911-913.
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