Ultra-low power 32-bit pipelined adder using subthreshold source-coupled logic with 5 fJ/stage PDP

Armin Tajalli, Elizabeth Brauer, Yusuf Leblebici

Research output: Contribution to journalArticle

8 Citations (Scopus)

Abstract

This article presents a new approach for improving the power-delay performance of subthreshold source-couple logic (STSCL) circuits. Using a simple two-phase pipelining technique, it is possible to increase the activity rate of STSCL gates with negligible additional cost, and hence reduce the total system energy consumption per operation. In the proposed pipelined topology, each STSCL gate is followed by a simple cross-coupled differential pair operating as a state keeper with a very low power consumption and small area overhead. Measurement results on a 32-bit pipelined adder chain fabricated with 0.18 μ m CMOS technology show that the proposed approach can achieve a significant reduction in power-delay product (PDP) down to 5 fJ/stage.

Original languageEnglish (US)
Pages (from-to)973-978
Number of pages6
JournalMicroelectronics Journal
Volume40
Issue number6
DOIs
StatePublished - Jun 2009

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Logic gates
Adders
logic
Logic circuits
products
logic circuits
Electric power utilization
Energy utilization
Topology
energy consumption
CMOS
topology
costs
Costs

Keywords

  • CMOS integrated circuits
  • Current-mode logic (CML)
  • Pipelined SCL
  • Source-coupled logic (SCL)
  • Subthreshold SCL (STSCL)
  • Ultra-low power circuit design

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Surfaces, Coatings and Films
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics

Cite this

Ultra-low power 32-bit pipelined adder using subthreshold source-coupled logic with 5 fJ/stage PDP. / Tajalli, Armin; Brauer, Elizabeth; Leblebici, Yusuf.

In: Microelectronics Journal, Vol. 40, No. 6, 06.2009, p. 973-978.

Research output: Contribution to journalArticle

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