Subthreshold source-coupled logic circuits for ultra-low-power applications

Armin Tajalli, Elizabeth J. Brauer, Yusuf Leblebici, Eric Vittoz

Research output: Contribution to journalArticle

77 Scopus citations

Abstract

This paper presents a novel approach for implementing ultra-low-power digital components and systems using source-coupled logic (SCL) circuit topology, operating in weak inversion (subthreshold) regime. Minimum size pMOS transistors with shorted drain-substrate contacts are used as gate-controlled, very high resistivity load devices. Based on the proposed approach, the power consumption and the operation frequency of logic circuits can be scaled down linearly by changing the tail bias current of SCL gates over a very wide range spanning several orders of magnitude, which is not achievable in subthreshold CMOS circuits. Measurements in conventional 0.18 μm CMOS technology show that the tail bias current of each gate can be set as low as 10 pA, with a supply voltage of 300 mV, resulting in a power-delay product of less than 1 fJ. Fundamental circuits such as ring oscillators and frequency dividers, as well as more complex digital blocks such as parallel multipliers designed by using the STSCL topology have been experimentally characterized.

Original languageEnglish (US)
Article number4550646
Pages (from-to)1699-1710
Number of pages12
JournalIEEE Journal of Solid-State Circuits
Volume43
Issue number7
DOIs
StatePublished - Jul 1 2008

Keywords

  • CMOS integrated circuits
  • CMOS logic circuit
  • Current-mode logic (CML)
  • Pipelining
  • Power-delay product
  • Source-coupled logic (SCL)
  • Subthreshold CMOS
  • Subthreshold SCL
  • Ultra-low-power circuits
  • Weak inversion

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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