Sub-70 PS full adder in 0.18 μm CMOS current-mode logic

Elizabeth Brauer, Yusuf Leblebici

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This paper presents a single-bit full adder in MOS Current-Mode Logic with fast delays and low power compared to configurations previously reported. Our low power full adder exhibits post-layout carry-in to carry-out delays of less than 70 ps and can be utilized as building blocks in very high performance datapaths. The circuits are designed and simulated in a 0.18 μm CMOS process and VDD of 1.8 V.

Original languageEnglish (US)
Title of host publicationProceedings of the IASTED International Conference on Circuits, Signals, and Systems
EditorsM.H. Rashid
Pages482-486
Number of pages5
StatePublished - 2004
EventProceedings of the IASTED International Conference on Circuits, Signals, and Systems - Clearwater Beach, FL, United States
Duration: Nov 28 2004Dec 1 2004

Other

OtherProceedings of the IASTED International Conference on Circuits, Signals, and Systems
CountryUnited States
CityClearwater Beach, FL
Period11/28/0412/1/04

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Networks (circuits)

Keywords

  • CML
  • CMOS
  • Current-mode logic
  • Full adder

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Brauer, E., & Leblebici, Y. (2004). Sub-70 PS full adder in 0.18 μm CMOS current-mode logic. In M. H. Rashid (Ed.), Proceedings of the IASTED International Conference on Circuits, Signals, and Systems (pp. 482-486). [449-101]

Sub-70 PS full adder in 0.18 μm CMOS current-mode logic. / Brauer, Elizabeth; Leblebici, Yusuf.

Proceedings of the IASTED International Conference on Circuits, Signals, and Systems. ed. / M.H. Rashid. 2004. p. 482-486 449-101.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Brauer, E & Leblebici, Y 2004, Sub-70 PS full adder in 0.18 μm CMOS current-mode logic. in MH Rashid (ed.), Proceedings of the IASTED International Conference on Circuits, Signals, and Systems., 449-101, pp. 482-486, Proceedings of the IASTED International Conference on Circuits, Signals, and Systems, Clearwater Beach, FL, United States, 11/28/04.
Brauer E, Leblebici Y. Sub-70 PS full adder in 0.18 μm CMOS current-mode logic. In Rashid MH, editor, Proceedings of the IASTED International Conference on Circuits, Signals, and Systems. 2004. p. 482-486. 449-101
Brauer, Elizabeth ; Leblebici, Yusuf. / Sub-70 PS full adder in 0.18 μm CMOS current-mode logic. Proceedings of the IASTED International Conference on Circuits, Signals, and Systems. editor / M.H. Rashid. 2004. pp. 482-486
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