Low noise MCML prefix adders using 0.18 μm CMOS technology

Elizabeth Brauer, Yusuf Leblebici

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

This paper presents 3 adders of 8, 16 and 32 bit operands using MOS Current-Mode Logic in a prefix adder architecture with minimum logic levels and fan-out of two. The 32-bit adder exhibits delays of less than 530 ps for nominal conditions with a power supply current spike of only 1.2% of the nominal current. The circuits are designed and simulated in a 0.18 μm CMOS process and VDD of 1.8V.

Original languageEnglish (US)
Title of host publicationProceedings of the IASTED International Conference on Circuits, Signals, and Systems
EditorsM.H. Rashid
Pages467-470
Number of pages4
StatePublished - 2004
EventProceedings of the IASTED International Conference on Circuits, Signals, and Systems - Clearwater Beach, FL, United States
Duration: Nov 28 2004Dec 1 2004

Other

OtherProceedings of the IASTED International Conference on Circuits, Signals, and Systems
CountryUnited States
CityClearwater Beach, FL
Period11/28/0412/1/04

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Keywords

  • CMOS
  • Current-mode logic
  • Low noise
  • MCML
  • Prefix adder

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Brauer, E., & Leblebici, Y. (2004). Low noise MCML prefix adders using 0.18 μm CMOS technology. In M. H. Rashid (Ed.), Proceedings of the IASTED International Conference on Circuits, Signals, and Systems (pp. 467-470). [449-103]