Improving the power-delay product in SCL circuits using source follower output stage

Armin Tajalli, Frank K. Gurkaynak, Yusuf Leblebici, Massimo Alioto, Elizabeth J. Brauer

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations

Abstract

This article explores the effect of using source follower buffers (SFB) at the output of source coupled logic (SCL) circuits. This technique can help to improve the power-delay product (PDP) of an SCL gate approximately by a factor of two. The proposed approach has been applied to improve the PDP in sub-threshold SCL circuits that have been developed for ultra-low power applications. Designed in conventional digital 0.18μm CMOS technology, the proposed SCL gate utilizing SFB at the output achieves a PDP of 0.5fJ/fF/gate while the gate draws 10nA from a 0.6V supply voltage.

Original languageEnglish (US)
Title of host publication2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
Pages145-148
Number of pages4
DOIs
StatePublished - Sep 19 2008
Event2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 - Seattle, WA, United States
Duration: May 18 2008May 21 2008

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Other

Other2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
CountryUnited States
CitySeattle, WA
Period5/18/085/21/08

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Tajalli, A., Gurkaynak, F. K., Leblebici, Y., Alioto, M., & Brauer, E. J. (2008). Improving the power-delay product in SCL circuits using source follower output stage. In 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 (pp. 145-148). [4541375] (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2008.4541375