Abstract
This article explores the effect of using source follower buffers (SFB) at the output of source coupled logic (SCL) circuits. This technique can help to improve the power-delay product (PDP) of an SCL gate approximately by a factor of two. The proposed approach has been applied to improve the PDP in sub-threshold SCL circuits that have been developed for ultra-low power applications. Designed in conventional digital 0.18μm CMOS technology, the proposed SCL gate utilizing SFB at the output achieves a PDP of 0.5fJ/fF/gate while the gate draws 10nA from a 0.6V supply voltage.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings - IEEE International Symposium on Circuits and Systems |
| Pages | 145-148 |
| Number of pages | 4 |
| DOIs | |
| State | Published - 2008 |
| Event | 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 - Seattle, WA, United States Duration: May 18 2008 → May 21 2008 |
Other
| Other | 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 |
|---|---|
| Country | United States |
| City | Seattle, WA |
| Period | 5/18/08 → 5/21/08 |
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ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
Cite this
Improving the power-delay product in SCL circuits using source follower output stage. / Tajalli, Armin; Gurkaynak, Frank K.; Leblebici, Yusuf; Alioto, Massimo; Brauer, Elizabeth.
Proceedings - IEEE International Symposium on Circuits and Systems. 2008. p. 145-148 4541375.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Improving the power-delay product in SCL circuits using source follower output stage
AU - Tajalli, Armin
AU - Gurkaynak, Frank K.
AU - Leblebici, Yusuf
AU - Alioto, Massimo
AU - Brauer, Elizabeth
PY - 2008
Y1 - 2008
N2 - This article explores the effect of using source follower buffers (SFB) at the output of source coupled logic (SCL) circuits. This technique can help to improve the power-delay product (PDP) of an SCL gate approximately by a factor of two. The proposed approach has been applied to improve the PDP in sub-threshold SCL circuits that have been developed for ultra-low power applications. Designed in conventional digital 0.18μm CMOS technology, the proposed SCL gate utilizing SFB at the output achieves a PDP of 0.5fJ/fF/gate while the gate draws 10nA from a 0.6V supply voltage.
AB - This article explores the effect of using source follower buffers (SFB) at the output of source coupled logic (SCL) circuits. This technique can help to improve the power-delay product (PDP) of an SCL gate approximately by a factor of two. The proposed approach has been applied to improve the PDP in sub-threshold SCL circuits that have been developed for ultra-low power applications. Designed in conventional digital 0.18μm CMOS technology, the proposed SCL gate utilizing SFB at the output achieves a PDP of 0.5fJ/fF/gate while the gate draws 10nA from a 0.6V supply voltage.
UR - http://www.scopus.com/inward/record.url?scp=51749085103&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=51749085103&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2008.4541375
DO - 10.1109/ISCAS.2008.4541375
M3 - Conference contribution
SN - 9781424416844
SP - 145
EP - 148
BT - Proceedings - IEEE International Symposium on Circuits and Systems
ER -