Improving the power-delay performance in subthreshold source-coupled logic circuits

Armin Tajalli, Massimo Alioto, Elizabeth J. Brauer, Yusuf Leblebici

Research output: Contribution to journalArticle

Abstract

Subthreshold source-coupled logic (STSCL) circuits can be used in design of low-voltage and ultra-low power digital systems. This article introduces and analyzes new techniques for implementing complex digital systems using STSCL gates with an improved power-delay product (PDP) based on source-follower output stages. A test chip has been manufactured in a conventional digital 0.18μm CMOS technology to evaluate the performance of the proposed STSCL circuit, and speed and PDP improvements by a factor of up to 2.4 were demonstrated.

Fingerprint

Coupled circuits
Logic circuits
Logic
Logic gates
Low Voltage
Electric potential
Chip
Evaluate
Output

ASJC Scopus subject areas

  • Computer Science(all)
  • Theoretical Computer Science

Cite this

@article{42e4abd345aa46c7b140e6b4035fc4a5,
title = "Improving the power-delay performance in subthreshold source-coupled logic circuits",
abstract = "Subthreshold source-coupled logic (STSCL) circuits can be used in design of low-voltage and ultra-low power digital systems. This article introduces and analyzes new techniques for implementing complex digital systems using STSCL gates with an improved power-delay product (PDP) based on source-follower output stages. A test chip has been manufactured in a conventional digital 0.18μm CMOS technology to evaluate the performance of the proposed STSCL circuit, and speed and PDP improvements by a factor of up to 2.4 were demonstrated.",
author = "Armin Tajalli and Massimo Alioto and Brauer, {Elizabeth J.} and Yusuf Leblebici",
year = "2009",
doi = "10.1007/978-3-540-95948-9_3",
language = "English (US)",
volume = "5349 LNCS",
pages = "21--30",
journal = "Lecture Notes in Computer Science",
issn = "0302-9743",
publisher = "Springer Verlag",

}

TY - JOUR

T1 - Improving the power-delay performance in subthreshold source-coupled logic circuits

AU - Tajalli, Armin

AU - Alioto, Massimo

AU - Brauer, Elizabeth J.

AU - Leblebici, Yusuf

PY - 2009

Y1 - 2009

N2 - Subthreshold source-coupled logic (STSCL) circuits can be used in design of low-voltage and ultra-low power digital systems. This article introduces and analyzes new techniques for implementing complex digital systems using STSCL gates with an improved power-delay product (PDP) based on source-follower output stages. A test chip has been manufactured in a conventional digital 0.18μm CMOS technology to evaluate the performance of the proposed STSCL circuit, and speed and PDP improvements by a factor of up to 2.4 were demonstrated.

AB - Subthreshold source-coupled logic (STSCL) circuits can be used in design of low-voltage and ultra-low power digital systems. This article introduces and analyzes new techniques for implementing complex digital systems using STSCL gates with an improved power-delay product (PDP) based on source-follower output stages. A test chip has been manufactured in a conventional digital 0.18μm CMOS technology to evaluate the performance of the proposed STSCL circuit, and speed and PDP improvements by a factor of up to 2.4 were demonstrated.

UR - http://www.scopus.com/inward/record.url?scp=61649111834&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=61649111834&partnerID=8YFLogxK

U2 - 10.1007/978-3-540-95948-9_3

DO - 10.1007/978-3-540-95948-9_3

M3 - Article

VL - 5349 LNCS

SP - 21

EP - 30

JO - Lecture Notes in Computer Science

JF - Lecture Notes in Computer Science

SN - 0302-9743

ER -