Improving the power-delay performance in subthreshold source-coupled logic circuits

Armin Tajalli, Massimo Alioto, Elizabeth J. Brauer, Yusuf Leblebici

Research output: Contribution to journalConference article

Abstract

Subthreshold source-coupled logic (STSCL) circuits can be used in design of low-voltage and ultra-low power digital systems. This article introduces and analyzes new techniques for implementing complex digital systems using STSCL gates with an improved power-delay product (PDP) based on source-follower output stages. A test chip has been manufactured in a conventional digital 0.18μm CMOS technology to evaluate the performance of the proposed STSCL circuit, and speed and PDP improvements by a factor of up to 2.4 were demonstrated.

Original languageEnglish (US)
Pages (from-to)21-30
Number of pages10
JournalLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume5349 LNCS
DOIs
StatePublished - Mar 11 2009
Event18th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2008 - Lisbon, Portugal
Duration: Sep 10 2008Sep 12 2008

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

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