Implementing ultra-high-value floating tunable CMOS resistors

A. Tajalli, Y. Leblebici, Elizabeth Brauer

Research output: Contribution to journalArticle

58 Citations (Scopus)

Abstract

A compact high-value floating resistor utilising PMOS devices in the subthreshold region is introduced. A test chip has been fabricated in 0.18m CMOS technology to verify the proposed concept. This technique has been applied to design a reconfigurable sixth-order very-low-cutoff-frequency MOSFET-C filter.

Original languageEnglish (US)
Pages (from-to)349-351
Number of pages3
JournalElectronics Letters
Volume44
Issue number5
DOIs
StatePublished - 2008

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Cutoff frequency
Resistors

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Implementing ultra-high-value floating tunable CMOS resistors. / Tajalli, A.; Leblebici, Y.; Brauer, Elizabeth.

In: Electronics Letters, Vol. 44, No. 5, 2008, p. 349-351.

Research output: Contribution to journalArticle

Tajalli, A. ; Leblebici, Y. ; Brauer, Elizabeth. / Implementing ultra-high-value floating tunable CMOS resistors. In: Electronics Letters. 2008 ; Vol. 44, No. 5. pp. 349-351.
@article{d8c4b116f9124ed98e852cf93dcdfcd4,
title = "Implementing ultra-high-value floating tunable CMOS resistors",
abstract = "A compact high-value floating resistor utilising PMOS devices in the subthreshold region is introduced. A test chip has been fabricated in 0.18m CMOS technology to verify the proposed concept. This technique has been applied to design a reconfigurable sixth-order very-low-cutoff-frequency MOSFET-C filter.",
author = "A. Tajalli and Y. Leblebici and Elizabeth Brauer",
year = "2008",
doi = "10.1049/el:20082538",
language = "English (US)",
volume = "44",
pages = "349--351",
journal = "Electronics Letters",
issn = "0013-5194",
publisher = "Institution of Engineering and Technology",
number = "5",

}

TY - JOUR

T1 - Implementing ultra-high-value floating tunable CMOS resistors

AU - Tajalli, A.

AU - Leblebici, Y.

AU - Brauer, Elizabeth

PY - 2008

Y1 - 2008

N2 - A compact high-value floating resistor utilising PMOS devices in the subthreshold region is introduced. A test chip has been fabricated in 0.18m CMOS technology to verify the proposed concept. This technique has been applied to design a reconfigurable sixth-order very-low-cutoff-frequency MOSFET-C filter.

AB - A compact high-value floating resistor utilising PMOS devices in the subthreshold region is introduced. A test chip has been fabricated in 0.18m CMOS technology to verify the proposed concept. This technique has been applied to design a reconfigurable sixth-order very-low-cutoff-frequency MOSFET-C filter.

UR - http://www.scopus.com/inward/record.url?scp=40149099350&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=40149099350&partnerID=8YFLogxK

U2 - 10.1049/el:20082538

DO - 10.1049/el:20082538

M3 - Article

VL - 44

SP - 349

EP - 351

JO - Electronics Letters

JF - Electronics Letters

SN - 0013-5194

IS - 5

ER -