Hardware implementation of a neural network pattern shaper algorithm

Elizabeth Brauer, James J. Abbas, Brian Callaway, Joshua Colvin, John Farris

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Electrical stimulation can be used to activate paralyzed muscles for the purpose of restoring motor functions such as stepping in individuals with spinal cord injury. Due to the variability observed in the responses of electrically stimulated muscles, several adaptive control techniques have been developed. The Pattern Shaper (PS) is an adaptive neural network that has been tested in a software implementation and has been shown to be capable of automatically generating cyclic patterns that are customized for an individual. The results of these tests are encouraging, but implementation of the real-time algorithm currently requires a dedicated PC. The purpose of this research is to develop a hardware implementation of a digital PS neural network to generate the electrical signals to stimulate muscles in individuals with spinal cord injury. In this work we have implemented the Pattern Shaper algorithm in hardware by mapping the digital logic circuit to a Field Programmable Gate Array (FPGA), developed a user interface to input data to the FPGA from a computer, and constructed a wire-wrapped board to implement the PS in hardware for use in clinical tests. This hardware implementation is a step towards the development of low-power, portable, adaptive controller that can be used in electrical stimulation systems.

Original languageEnglish (US)
Title of host publicationProceedings of the International Joint Conference on Neural Networks
PublisherIEEE
Pages2315-2318
Number of pages4
Volume4
StatePublished - 1999
EventInternational Joint Conference on Neural Networks (IJCNN'99) - Washington, DC, USA
Duration: Jul 10 1999Jul 16 1999

Other

OtherInternational Joint Conference on Neural Networks (IJCNN'99)
CityWashington, DC, USA
Period7/10/997/16/99

Fingerprint

Neural networks
Hardware
Muscle
Field programmable gate arrays (FPGA)
Logic circuits
Digital circuits
Printed circuit boards
User interfaces
Wire
Controllers

ASJC Scopus subject areas

  • Software

Cite this

Brauer, E., Abbas, J. J., Callaway, B., Colvin, J., & Farris, J. (1999). Hardware implementation of a neural network pattern shaper algorithm. In Proceedings of the International Joint Conference on Neural Networks (Vol. 4, pp. 2315-2318). IEEE.

Hardware implementation of a neural network pattern shaper algorithm. / Brauer, Elizabeth; Abbas, James J.; Callaway, Brian; Colvin, Joshua; Farris, John.

Proceedings of the International Joint Conference on Neural Networks. Vol. 4 IEEE, 1999. p. 2315-2318.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Brauer, E, Abbas, JJ, Callaway, B, Colvin, J & Farris, J 1999, Hardware implementation of a neural network pattern shaper algorithm. in Proceedings of the International Joint Conference on Neural Networks. vol. 4, IEEE, pp. 2315-2318, International Joint Conference on Neural Networks (IJCNN'99), Washington, DC, USA, 7/10/99.
Brauer E, Abbas JJ, Callaway B, Colvin J, Farris J. Hardware implementation of a neural network pattern shaper algorithm. In Proceedings of the International Joint Conference on Neural Networks. Vol. 4. IEEE. 1999. p. 2315-2318
Brauer, Elizabeth ; Abbas, James J. ; Callaway, Brian ; Colvin, Joshua ; Farris, John. / Hardware implementation of a neural network pattern shaper algorithm. Proceedings of the International Joint Conference on Neural Networks. Vol. 4 IEEE, 1999. pp. 2315-2318
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