Functional verification of ECL circuits including voltage regulators

Elizabeth Brauer, S. M. Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Three major steps in designing emitter-coupled logic (ECL) circuits are generating correct functional behavior, guaranteeing design rules are obeyed and verifying delay behavior. Previous ECL simulators have addressed the issue of delay behavior and thus indirectly considered functional behavior. Checking design rules has not been addressed. Previous ECL simulators have not included voltage regulators despite their important role in circuit function. In our functional verifier, the circuit partitioning module divides the circuit into current source trees and identifies voltage regulators. The reference voltages generated by the voltage regulators are calculated using electrical simulation techniques and a simplified Ebers-Moll transistor model is used to calculate current sharing in emitter-coupled transistors of the switching subcircuits. The functional verification approach introduced in this paper can be used to verify circuit functionality under varying operating conditions of power supply voltage, temperature and device parameters, and, in addition, to detect design errors such as deep transistor saturation, excessive emitter current and voltage margin violations. For an industrial benchmark circuit with 842 transistors, our functional verifier performs the functional simulation and detects design errors over 800 times faster than the DC and transient analysis of SPICE3.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherPubl by IEEE
Pages1710-1713
Number of pages4
Volume3
ISBN (Print)0780312813
StatePublished - 1993
Externally publishedYes
EventProceedings of the 1993 IEEE International Symposium on Circuits and Systems - Chicago, IL, USA
Duration: May 3 1993May 6 1993

Other

OtherProceedings of the 1993 IEEE International Symposium on Circuits and Systems
CityChicago, IL, USA
Period5/3/935/6/93

Fingerprint

Emitter coupled logic circuits
Voltage regulators
Transistors
Networks (circuits)
Electric potential
Simulators
Transient analysis

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Brauer, E., & Kang, S. M. (1993). Functional verification of ECL circuits including voltage regulators. In Proceedings - IEEE International Symposium on Circuits and Systems (Vol. 3, pp. 1710-1713). Publ by IEEE.

Functional verification of ECL circuits including voltage regulators. / Brauer, Elizabeth; Kang, S. M.

Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 3 Publ by IEEE, 1993. p. 1710-1713.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Brauer, E & Kang, SM 1993, Functional verification of ECL circuits including voltage regulators. in Proceedings - IEEE International Symposium on Circuits and Systems. vol. 3, Publ by IEEE, pp. 1710-1713, Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, Chicago, IL, USA, 5/3/93.
Brauer E, Kang SM. Functional verification of ECL circuits including voltage regulators. In Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 3. Publ by IEEE. 1993. p. 1710-1713
Brauer, Elizabeth ; Kang, S. M. / Functional verification of ECL circuits including voltage regulators. Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 3 Publ by IEEE, 1993. pp. 1710-1713
@inproceedings{589b286160ef4f1b994e494762f398fe,
title = "Functional verification of ECL circuits including voltage regulators",
abstract = "Three major steps in designing emitter-coupled logic (ECL) circuits are generating correct functional behavior, guaranteeing design rules are obeyed and verifying delay behavior. Previous ECL simulators have addressed the issue of delay behavior and thus indirectly considered functional behavior. Checking design rules has not been addressed. Previous ECL simulators have not included voltage regulators despite their important role in circuit function. In our functional verifier, the circuit partitioning module divides the circuit into current source trees and identifies voltage regulators. The reference voltages generated by the voltage regulators are calculated using electrical simulation techniques and a simplified Ebers-Moll transistor model is used to calculate current sharing in emitter-coupled transistors of the switching subcircuits. The functional verification approach introduced in this paper can be used to verify circuit functionality under varying operating conditions of power supply voltage, temperature and device parameters, and, in addition, to detect design errors such as deep transistor saturation, excessive emitter current and voltage margin violations. For an industrial benchmark circuit with 842 transistors, our functional verifier performs the functional simulation and detects design errors over 800 times faster than the DC and transient analysis of SPICE3.",
author = "Elizabeth Brauer and Kang, {S. M.}",
year = "1993",
language = "English (US)",
isbn = "0780312813",
volume = "3",
pages = "1710--1713",
booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Publ by IEEE",

}

TY - GEN

T1 - Functional verification of ECL circuits including voltage regulators

AU - Brauer, Elizabeth

AU - Kang, S. M.

PY - 1993

Y1 - 1993

N2 - Three major steps in designing emitter-coupled logic (ECL) circuits are generating correct functional behavior, guaranteeing design rules are obeyed and verifying delay behavior. Previous ECL simulators have addressed the issue of delay behavior and thus indirectly considered functional behavior. Checking design rules has not been addressed. Previous ECL simulators have not included voltage regulators despite their important role in circuit function. In our functional verifier, the circuit partitioning module divides the circuit into current source trees and identifies voltage regulators. The reference voltages generated by the voltage regulators are calculated using electrical simulation techniques and a simplified Ebers-Moll transistor model is used to calculate current sharing in emitter-coupled transistors of the switching subcircuits. The functional verification approach introduced in this paper can be used to verify circuit functionality under varying operating conditions of power supply voltage, temperature and device parameters, and, in addition, to detect design errors such as deep transistor saturation, excessive emitter current and voltage margin violations. For an industrial benchmark circuit with 842 transistors, our functional verifier performs the functional simulation and detects design errors over 800 times faster than the DC and transient analysis of SPICE3.

AB - Three major steps in designing emitter-coupled logic (ECL) circuits are generating correct functional behavior, guaranteeing design rules are obeyed and verifying delay behavior. Previous ECL simulators have addressed the issue of delay behavior and thus indirectly considered functional behavior. Checking design rules has not been addressed. Previous ECL simulators have not included voltage regulators despite their important role in circuit function. In our functional verifier, the circuit partitioning module divides the circuit into current source trees and identifies voltage regulators. The reference voltages generated by the voltage regulators are calculated using electrical simulation techniques and a simplified Ebers-Moll transistor model is used to calculate current sharing in emitter-coupled transistors of the switching subcircuits. The functional verification approach introduced in this paper can be used to verify circuit functionality under varying operating conditions of power supply voltage, temperature and device parameters, and, in addition, to detect design errors such as deep transistor saturation, excessive emitter current and voltage margin violations. For an industrial benchmark circuit with 842 transistors, our functional verifier performs the functional simulation and detects design errors over 800 times faster than the DC and transient analysis of SPICE3.

UR - http://www.scopus.com/inward/record.url?scp=0027235198&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0027235198&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0027235198

SN - 0780312813

VL - 3

SP - 1710

EP - 1713

BT - Proceedings - IEEE International Symposium on Circuits and Systems

PB - Publ by IEEE

ER -