Abstract
Three major steps in designing emitter-coupled logic (ECL) circuits are generating correct functional behavior, guaranteeing design rules are obeyed and verifying delay behavior. Previous ECL simulators have addressed the issue of delay behavior and thus indirectly considered functional behavior. Checking design rules has not been addressed. Previous ECL simulators have not included voltage regulators despite their important role in circuit function. In our functional verifier, the circuit partitioning module divides the circuit into current source trees and identifies voltage regulators. The reference voltages generated by the voltage regulators are calculated using electrical simulation techniques and a simplified Ebers-Moll transistor model is used to calculate current sharing in emitter-coupled transistors of the switching subcircuits. The functional verification approach introduced in this paper can be used to verify circuit functionality under varying operating conditions of power supply voltage, temperature and device parameters, and, in addition, to detect design errors such as deep transistor saturation, excessive emitter current and voltage margin violations. For an industrial benchmark circuit with 842 transistors, our functional verifier performs the functional simulation and detects design errors over 800 times faster than the DC and transient analysis of SPICE3.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings - IEEE International Symposium on Circuits and Systems |
| Publisher | Publ by IEEE |
| Pages | 1710-1713 |
| Number of pages | 4 |
| Volume | 3 |
| ISBN (Print) | 0780312813 |
| State | Published - 1993 |
| Externally published | Yes |
| Event | Proceedings of the 1993 IEEE International Symposium on Circuits and Systems - Chicago, IL, USA Duration: May 3 1993 → May 6 1993 |
Other
| Other | Proceedings of the 1993 IEEE International Symposium on Circuits and Systems |
|---|---|
| City | Chicago, IL, USA |
| Period | 5/3/93 → 5/6/93 |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials
Cite this
Functional verification of ECL circuits including voltage regulators. / Brauer, Elizabeth; Kang, S. M.
Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 3 Publ by IEEE, 1993. p. 1710-1713.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Functional verification of ECL circuits including voltage regulators
AU - Brauer, Elizabeth
AU - Kang, S. M.
PY - 1993
Y1 - 1993
N2 - Three major steps in designing emitter-coupled logic (ECL) circuits are generating correct functional behavior, guaranteeing design rules are obeyed and verifying delay behavior. Previous ECL simulators have addressed the issue of delay behavior and thus indirectly considered functional behavior. Checking design rules has not been addressed. Previous ECL simulators have not included voltage regulators despite their important role in circuit function. In our functional verifier, the circuit partitioning module divides the circuit into current source trees and identifies voltage regulators. The reference voltages generated by the voltage regulators are calculated using electrical simulation techniques and a simplified Ebers-Moll transistor model is used to calculate current sharing in emitter-coupled transistors of the switching subcircuits. The functional verification approach introduced in this paper can be used to verify circuit functionality under varying operating conditions of power supply voltage, temperature and device parameters, and, in addition, to detect design errors such as deep transistor saturation, excessive emitter current and voltage margin violations. For an industrial benchmark circuit with 842 transistors, our functional verifier performs the functional simulation and detects design errors over 800 times faster than the DC and transient analysis of SPICE3.
AB - Three major steps in designing emitter-coupled logic (ECL) circuits are generating correct functional behavior, guaranteeing design rules are obeyed and verifying delay behavior. Previous ECL simulators have addressed the issue of delay behavior and thus indirectly considered functional behavior. Checking design rules has not been addressed. Previous ECL simulators have not included voltage regulators despite their important role in circuit function. In our functional verifier, the circuit partitioning module divides the circuit into current source trees and identifies voltage regulators. The reference voltages generated by the voltage regulators are calculated using electrical simulation techniques and a simplified Ebers-Moll transistor model is used to calculate current sharing in emitter-coupled transistors of the switching subcircuits. The functional verification approach introduced in this paper can be used to verify circuit functionality under varying operating conditions of power supply voltage, temperature and device parameters, and, in addition, to detect design errors such as deep transistor saturation, excessive emitter current and voltage margin violations. For an industrial benchmark circuit with 842 transistors, our functional verifier performs the functional simulation and detects design errors over 800 times faster than the DC and transient analysis of SPICE3.
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UR - http://www.scopus.com/inward/citedby.url?scp=0027235198&partnerID=8YFLogxK
M3 - Conference contribution
SN - 0780312813
VL - 3
SP - 1710
EP - 1713
BT - Proceedings - IEEE International Symposium on Circuits and Systems
PB - Publ by IEEE
ER -