Finding efficient inductor geometries in digital CMOS process for RF applications

Elizabeth Brauer, Vikram Magoon

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Genetic algorithms, robust search tools based on biological selection and reproduction, are used to find efficient planar inductor geometries, which meet the specifications of inductance value and quality factor and require a small chip area. We consider a specific example using a standard digital CMOS process with 6 layers of metal.

Original languageEnglish (US)
Title of host publicationProceedings of the IASTED International Conference on Circuits, Signals, and Systems
EditorsM.H. Rashid
Pages558-561
Number of pages4
StatePublished - 2004
EventProceedings of the IASTED International Conference on Circuits, Signals, and Systems - Clearwater Beach, FL, United States
Duration: Nov 28 2004Dec 1 2004

Other

OtherProceedings of the IASTED International Conference on Circuits, Signals, and Systems
CountryUnited States
CityClearwater Beach, FL
Period11/28/0412/1/04

Fingerprint

Inductance
Genetic algorithms
Specifications
Geometry
Metals

Keywords

  • CMOS
  • Genetic algorithms
  • Inductor
  • RF

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Brauer, E., & Magoon, V. (2004). Finding efficient inductor geometries in digital CMOS process for RF applications. In M. H. Rashid (Ed.), Proceedings of the IASTED International Conference on Circuits, Signals, and Systems (pp. 558-561). [449-048]

Finding efficient inductor geometries in digital CMOS process for RF applications. / Brauer, Elizabeth; Magoon, Vikram.

Proceedings of the IASTED International Conference on Circuits, Signals, and Systems. ed. / M.H. Rashid. 2004. p. 558-561 449-048.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Brauer, E & Magoon, V 2004, Finding efficient inductor geometries in digital CMOS process for RF applications. in MH Rashid (ed.), Proceedings of the IASTED International Conference on Circuits, Signals, and Systems., 449-048, pp. 558-561, Proceedings of the IASTED International Conference on Circuits, Signals, and Systems, Clearwater Beach, FL, United States, 11/28/04.
Brauer E, Magoon V. Finding efficient inductor geometries in digital CMOS process for RF applications. In Rashid MH, editor, Proceedings of the IASTED International Conference on Circuits, Signals, and Systems. 2004. p. 558-561. 449-048
Brauer, Elizabeth ; Magoon, Vikram. / Finding efficient inductor geometries in digital CMOS process for RF applications. Proceedings of the IASTED International Conference on Circuits, Signals, and Systems. editor / M.H. Rashid. 2004. pp. 558-561
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