Abstract
This brief examines different parity-check node decoding algorithms for low-density parity-check (LDPC) codes, seeking to recoup the performance loss incurred by the min-sum approximation compared to sum–product decoding. Two degree-matched check node decoding approximations that depend on the check node degree dc are presented. Both have low complexity and can be applied to any degree distribution. Simulation results show near sum–product decoding performance for both degree-matched check node approximations for regular and irregular LDPCs.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 1054-1058 |
| Number of pages | 5 |
| Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
| Volume | 53 |
| Issue number | 10 |
| DOIs | |
| State | Published - Oct 2006 |
| Externally published | Yes |
Keywords
- Iterative decoding
- LDPC codes
- reduced-complexity decoding
ASJC Scopus subject areas
- Electrical and Electronic Engineering
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Cite this
Howard, S. L., Schlegel, C., & Gaudet, V. C. (2006). Degree-Matched Check Node Decoding for Regular and Irregular LDPCs. IEEE Transactions on Circuits and Systems II: Express Briefs, 53(10), 1054-1058. https://doi.org/10.1109/TCSII.2006.882204