Analytic method to calculate emitter follower delay using trial functions in coupled node equations

Elizabeth Brauer, S. M. Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We use a quasi-linear large-signal bipolar junction transistor model and node waveform trial functions in coupled node equations to calculate delay of emitter followers driving fan-out gates and interconnect resistance and capacitance.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Editors Anon
PublisherIEEE
Pages1580-1583
Number of pages4
Volume3
StatePublished - 1995
Externally publishedYes
EventProceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) - Seattle, WA, USA
Duration: Apr 30 1995May 3 1995

Other

OtherProceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3)
CitySeattle, WA, USA
Period4/30/955/3/95

Fingerprint

Bipolar transistors
Fans
Capacitance

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Brauer, E., & Kang, S. M. (1995). Analytic method to calculate emitter follower delay using trial functions in coupled node equations. In Anon (Ed.), Proceedings - IEEE International Symposium on Circuits and Systems (Vol. 3, pp. 1580-1583). IEEE.

Analytic method to calculate emitter follower delay using trial functions in coupled node equations. / Brauer, Elizabeth; Kang, S. M.

Proceedings - IEEE International Symposium on Circuits and Systems. ed. / Anon. Vol. 3 IEEE, 1995. p. 1580-1583.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Brauer, E & Kang, SM 1995, Analytic method to calculate emitter follower delay using trial functions in coupled node equations. in Anon (ed.), Proceedings - IEEE International Symposium on Circuits and Systems. vol. 3, IEEE, pp. 1580-1583, Proceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3), Seattle, WA, USA, 4/30/95.
Brauer E, Kang SM. Analytic method to calculate emitter follower delay using trial functions in coupled node equations. In Anon, editor, Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 3. IEEE. 1995. p. 1580-1583
Brauer, Elizabeth ; Kang, S. M. / Analytic method to calculate emitter follower delay using trial functions in coupled node equations. Proceedings - IEEE International Symposium on Circuits and Systems. editor / Anon. Vol. 3 IEEE, 1995. pp. 1580-1583
@inproceedings{8f47248d7ee34961a59e76062b87d086,
title = "Analytic method to calculate emitter follower delay using trial functions in coupled node equations",
abstract = "We use a quasi-linear large-signal bipolar junction transistor model and node waveform trial functions in coupled node equations to calculate delay of emitter followers driving fan-out gates and interconnect resistance and capacitance.",
author = "Elizabeth Brauer and Kang, {S. M.}",
year = "1995",
language = "English (US)",
volume = "3",
pages = "1580--1583",
editor = "Anon",
booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "IEEE",

}

TY - GEN

T1 - Analytic method to calculate emitter follower delay using trial functions in coupled node equations

AU - Brauer, Elizabeth

AU - Kang, S. M.

PY - 1995

Y1 - 1995

N2 - We use a quasi-linear large-signal bipolar junction transistor model and node waveform trial functions in coupled node equations to calculate delay of emitter followers driving fan-out gates and interconnect resistance and capacitance.

AB - We use a quasi-linear large-signal bipolar junction transistor model and node waveform trial functions in coupled node equations to calculate delay of emitter followers driving fan-out gates and interconnect resistance and capacitance.

UR - http://www.scopus.com/inward/record.url?scp=0029192779&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0029192779&partnerID=8YFLogxK

M3 - Conference contribution

VL - 3

SP - 1580

EP - 1583

BT - Proceedings - IEEE International Symposium on Circuits and Systems

A2 - Anon, null

PB - IEEE

ER -