Analytic method to calculate emitter follower delay using trial functions in coupled node equations

E. J. Brauer, S. M. Kang

Research output: Contribution to journalConference article

Abstract

We use a quasi-linear large-signal bipolar junction transistor model and node waveform trial functions in coupled node equations to calculate delay of emitter followers driving fan-out gates and interconnect resistance and capacitance.

Original languageEnglish (US)
Pages (from-to)1580-1583
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume3
StatePublished - Jan 1 1995
Externally publishedYes
EventProceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) - Seattle, WA, USA
Duration: Apr 30 1995May 3 1995

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Analytic method to calculate emitter follower delay using trial functions in coupled node equations'. Together they form a unique fingerprint.

  • Cite this