Analytic method to calculate emitter follower delay using trial functions in coupled node equations

Elizabeth Brauer, S. M. Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We use a quasi-linear large-signal bipolar junction transistor model and node waveform trial functions in coupled node equations to calculate delay of emitter followers driving fan-out gates and interconnect resistance and capacitance.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Editors Anon
PublisherIEEE
Pages1580-1583
Number of pages4
Volume3
StatePublished - 1995
Externally publishedYes
EventProceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) - Seattle, WA, USA
Duration: Apr 30 1995May 3 1995

Other

OtherProceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3)
CitySeattle, WA, USA
Period4/30/955/3/95

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Brauer, E., & Kang, S. M. (1995). Analytic method to calculate emitter follower delay using trial functions in coupled node equations. In Anon (Ed.), Proceedings - IEEE International Symposium on Circuits and Systems (Vol. 3, pp. 1580-1583). IEEE.