An Algorithm for Functional Verification of Digital ECL Circuits

Research output: Contribution to journalArticle

Abstract

In recent years, silicon bipolar junction transistors (BJT) have been scaled down significantly with improved switching characteristics. Consequently, emitter-coupled logic (ECL) circuits have reduced power consumption while maintaining their speed advantage over other circuit technologies. The development of very large scale ECL circuits requires advanced computer-aided design tools. In this paper, we present a new computationally efficient algorithm for functional verification of a broad class of digital ECL circuits. The functional verification algorithm uses the transistor level circuit description to calculate steady-state device currents and node voltages of switching subcircuits. Voltage regulators are identified automatically for electrical simulation. A simplified Ebers–Moll BJT model is used to calculate current sharing in emitter-coupled transistors analytically and to detect design errors such as deep transistor saturation, excessive emitter current, and voltage margin violations. Our algorithm provides a significant saving in CPU time with accuracy comparable to SPICE in the calculation of steady-state voltages.

Original languageEnglish (US)
Pages (from-to)1546-1556
Number of pages11
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume14
Issue number12
DOIs
StatePublished - 1995
Externally publishedYes

Fingerprint

Emitter coupled logic circuits
Transistors
Bipolar transistors
Electric potential
Voltage regulators
Networks (circuits)
SPICE
Program processors
Computer aided design
Electric power utilization
Silicon

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Software
  • Electrical and Electronic Engineering
  • Computational Theory and Mathematics
  • Computer Science Applications
  • Hardware and Architecture

Cite this

@article{d7e316e56b854c4d90e03b2551e0df93,
title = "An Algorithm for Functional Verification of Digital ECL Circuits",
abstract = "In recent years, silicon bipolar junction transistors (BJT) have been scaled down significantly with improved switching characteristics. Consequently, emitter-coupled logic (ECL) circuits have reduced power consumption while maintaining their speed advantage over other circuit technologies. The development of very large scale ECL circuits requires advanced computer-aided design tools. In this paper, we present a new computationally efficient algorithm for functional verification of a broad class of digital ECL circuits. The functional verification algorithm uses the transistor level circuit description to calculate steady-state device currents and node voltages of switching subcircuits. Voltage regulators are identified automatically for electrical simulation. A simplified Ebers–Moll BJT model is used to calculate current sharing in emitter-coupled transistors analytically and to detect design errors such as deep transistor saturation, excessive emitter current, and voltage margin violations. Our algorithm provides a significant saving in CPU time with accuracy comparable to SPICE in the calculation of steady-state voltages.",
author = "Elizabeth Brauer",
year = "1995",
doi = "10.1109/43.476584",
language = "English (US)",
volume = "14",
pages = "1546--1556",
journal = "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",
issn = "0278-0070",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "12",

}

TY - JOUR

T1 - An Algorithm for Functional Verification of Digital ECL Circuits

AU - Brauer, Elizabeth

PY - 1995

Y1 - 1995

N2 - In recent years, silicon bipolar junction transistors (BJT) have been scaled down significantly with improved switching characteristics. Consequently, emitter-coupled logic (ECL) circuits have reduced power consumption while maintaining their speed advantage over other circuit technologies. The development of very large scale ECL circuits requires advanced computer-aided design tools. In this paper, we present a new computationally efficient algorithm for functional verification of a broad class of digital ECL circuits. The functional verification algorithm uses the transistor level circuit description to calculate steady-state device currents and node voltages of switching subcircuits. Voltage regulators are identified automatically for electrical simulation. A simplified Ebers–Moll BJT model is used to calculate current sharing in emitter-coupled transistors analytically and to detect design errors such as deep transistor saturation, excessive emitter current, and voltage margin violations. Our algorithm provides a significant saving in CPU time with accuracy comparable to SPICE in the calculation of steady-state voltages.

AB - In recent years, silicon bipolar junction transistors (BJT) have been scaled down significantly with improved switching characteristics. Consequently, emitter-coupled logic (ECL) circuits have reduced power consumption while maintaining their speed advantage over other circuit technologies. The development of very large scale ECL circuits requires advanced computer-aided design tools. In this paper, we present a new computationally efficient algorithm for functional verification of a broad class of digital ECL circuits. The functional verification algorithm uses the transistor level circuit description to calculate steady-state device currents and node voltages of switching subcircuits. Voltage regulators are identified automatically for electrical simulation. A simplified Ebers–Moll BJT model is used to calculate current sharing in emitter-coupled transistors analytically and to detect design errors such as deep transistor saturation, excessive emitter current, and voltage margin violations. Our algorithm provides a significant saving in CPU time with accuracy comparable to SPICE in the calculation of steady-state voltages.

UR - http://www.scopus.com/inward/record.url?scp=0029491086&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0029491086&partnerID=8YFLogxK

U2 - 10.1109/43.476584

DO - 10.1109/43.476584

M3 - Article

AN - SCOPUS:0029491086

VL - 14

SP - 1546

EP - 1556

JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

SN - 0278-0070

IS - 12

ER -