Adapting processor architectures for the periphery of the IoT nervous system

Paul G Flikkema, Bertrand Cambou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

We argue that the processor microarchitectures of today's microcontrollers are poorly matched to the computational workloads of IoT edge nodes, where largely independent chains of processes manage a dynamic mixture of periodic and sporadic tasks that must be executed in real time. Hardware support of priorities for some tasks and software support of priorities for others impedes efficient, correct design, and a single, monolithic ALU is a bottleneck for the diverse, asynchronous computational demands of these workloads. We describe a new processor microarchitecture with hardware support of unified fine-scale priorities for all processes, and with a dispatch-issue-execute pipeline supporting process-level parallelism. The datapath includes multiple functional units, enabling parallel processing via dynamic matching of resources to demand. The set of functional units includes computational assets that reflect the needs of IoT nodes, including a crypto-primitive generation engine.

Original languageEnglish (US)
Title of host publication2016 IEEE 3rd World Forum on Internet of Things, WF-IoT 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages615-620
Number of pages6
ISBN (Electronic)9781509041305
DOIs
StatePublished - Feb 6 2017
Event3rd IEEE World Forum on Internet of Things, WF-IoT 2016 - Reston, United States
Duration: Dec 12 2016Dec 14 2016

Other

Other3rd IEEE World Forum on Internet of Things, WF-IoT 2016
CountryUnited States
CityReston
Period12/12/1612/14/16

Fingerprint

Neurology
Hardware
Microcontrollers
Pipelines
Engines
Processing
Internet of things

Keywords

  • associative memory
  • atomicity
  • content addressable memory
  • crypto-primitive
  • decoding
  • dispatch
  • execute
  • functional unit
  • IoT
  • issue
  • MCU
  • microarchitecture
  • microcontroller
  • priority
  • process
  • processor
  • security

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Networks and Communications
  • Hardware and Architecture

Cite this

Flikkema, P. G., & Cambou, B. (2017). Adapting processor architectures for the periphery of the IoT nervous system. In 2016 IEEE 3rd World Forum on Internet of Things, WF-IoT 2016 (pp. 615-620). [7845427] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/WF-IoT.2016.7845427

Adapting processor architectures for the periphery of the IoT nervous system. / Flikkema, Paul G; Cambou, Bertrand.

2016 IEEE 3rd World Forum on Internet of Things, WF-IoT 2016. Institute of Electrical and Electronics Engineers Inc., 2017. p. 615-620 7845427.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Flikkema, PG & Cambou, B 2017, Adapting processor architectures for the periphery of the IoT nervous system. in 2016 IEEE 3rd World Forum on Internet of Things, WF-IoT 2016., 7845427, Institute of Electrical and Electronics Engineers Inc., pp. 615-620, 3rd IEEE World Forum on Internet of Things, WF-IoT 2016, Reston, United States, 12/12/16. https://doi.org/10.1109/WF-IoT.2016.7845427
Flikkema PG, Cambou B. Adapting processor architectures for the periphery of the IoT nervous system. In 2016 IEEE 3rd World Forum on Internet of Things, WF-IoT 2016. Institute of Electrical and Electronics Engineers Inc. 2017. p. 615-620. 7845427 https://doi.org/10.1109/WF-IoT.2016.7845427
Flikkema, Paul G ; Cambou, Bertrand. / Adapting processor architectures for the periphery of the IoT nervous system. 2016 IEEE 3rd World Forum on Internet of Things, WF-IoT 2016. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 615-620
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