A scalable LDPC decoder ASIC architecture with bit-serial message exchange

Tyler Brandon, Robert Hang, Gary Block, Vincent C. Gaudet, Bruce Cockburn, Sheryl L Howard, Christian Giasson, Keith Boyle, Paul Goud, Siavash Sheikh Zeinoddin, Anthony Rapley, Stephen Bates, Duncan Elliott, Christian Schlegel

Research output: Contribution to journalArticle

28 Citations (Scopus)

Abstract

We present a scalable bit-serial architecture for ASIC realizations of low-density parity check (LDPC) decoders. Supporting the architecture's potential, we describe a decoder implementation for a (256,128) regular-(3,6) LDPC code that has a decoded information throughput of 250 Mbps, a core area of 6.96 mm2 in 180-nm 6-metal CMOS, and an energy efficiency of 7.56 nJ per uncoded bit at low signal-to-noise ratios. The decoder is fully block-parallel, with all bits of each 256-bit codeword being processed by 256 variable nodes and 128 parity check nodes that together form an 8-stage iteration pipeline. Extrinsic messages are exchanged bit-serially between the variable and parity check nodes to significantly reduce the interleaver wiring. Parity check node processing is also bit-serial. The silicon implementation performs 32 iterations of the min-sum decoding algorithm on two staggered codewords in the same pipeline. The results of a supplementary layout study show that the reduced wiring congestion makes the decoder readily scaleable up to the longer kilobit-size LDPC codewords that appear in important emerging communication standards.

Original languageEnglish (US)
Pages (from-to)385-398
Number of pages14
JournalIntegration, the VLSI Journal
Volume41
Issue number3
DOIs
StatePublished - May 2008
Externally publishedYes

Fingerprint

Application specific integrated circuits
Electric wiring
Pipelines
Energy efficiency
Decoding
Signal to noise ratio
Throughput
Silicon
Communication
Processing
Metals

Keywords

  • Bit-serial arithmetic
  • Error-control codes
  • Iterative decoding
  • Low-density parity check codes

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

Cite this

Brandon, T., Hang, R., Block, G., Gaudet, V. C., Cockburn, B., Howard, S. L., ... Schlegel, C. (2008). A scalable LDPC decoder ASIC architecture with bit-serial message exchange. Integration, the VLSI Journal, 41(3), 385-398. https://doi.org/10.1016/j.vlsi.2007.07.003

A scalable LDPC decoder ASIC architecture with bit-serial message exchange. / Brandon, Tyler; Hang, Robert; Block, Gary; Gaudet, Vincent C.; Cockburn, Bruce; Howard, Sheryl L; Giasson, Christian; Boyle, Keith; Goud, Paul; Zeinoddin, Siavash Sheikh; Rapley, Anthony; Bates, Stephen; Elliott, Duncan; Schlegel, Christian.

In: Integration, the VLSI Journal, Vol. 41, No. 3, 05.2008, p. 385-398.

Research output: Contribution to journalArticle

Brandon, T, Hang, R, Block, G, Gaudet, VC, Cockburn, B, Howard, SL, Giasson, C, Boyle, K, Goud, P, Zeinoddin, SS, Rapley, A, Bates, S, Elliott, D & Schlegel, C 2008, 'A scalable LDPC decoder ASIC architecture with bit-serial message exchange', Integration, the VLSI Journal, vol. 41, no. 3, pp. 385-398. https://doi.org/10.1016/j.vlsi.2007.07.003
Brandon, Tyler ; Hang, Robert ; Block, Gary ; Gaudet, Vincent C. ; Cockburn, Bruce ; Howard, Sheryl L ; Giasson, Christian ; Boyle, Keith ; Goud, Paul ; Zeinoddin, Siavash Sheikh ; Rapley, Anthony ; Bates, Stephen ; Elliott, Duncan ; Schlegel, Christian. / A scalable LDPC decoder ASIC architecture with bit-serial message exchange. In: Integration, the VLSI Journal. 2008 ; Vol. 41, No. 3. pp. 385-398.
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