• 289 Citations
  • 8 h-Index
19922011

Research output per year

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Research Output

  • 289 Citations
  • 8 h-Index
  • 14 Conference contribution
  • 8 Article
  • 6 Paper
  • 6 Conference article
2011
2009

Ultra-low power 32-bit pipelined adder using subthreshold source-coupled logic with 5 fJ/stage PDP

Tajalli, A., Brauer, E. J. & Leblebici, Y., Jun 1 2009, In : Microelectronics Journal. 40, 6, p. 973-978 6 p.

Research output: Contribution to journalArticle

8 Scopus citations
2008

Implementing ultra-high-value floating tunable CMOS resistors

Tajalli, A., Leblebici, Y. & Brauer, E. J., Mar 7 2008, In : Electronics Letters. 44, 5, p. 349-351 3 p.

Research output: Contribution to journalArticle

62 Scopus citations

Improving the power-delay product in SCL circuits using source follower output stage

Tajalli, A., Gurkaynak, F. K., Leblebici, Y., Alioto, M. & Brauer, E. J., Sep 19 2008, 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008. p. 145-148 4 p. 4541375. (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations

Subthreshold source-coupled logic circuits for ultra-low-power applications

Tajalli, A., Brauer, E. J., Leblebici, Y. & Vittoz, E., Jul 1 2008, In : IEEE Journal of Solid-State Circuits. 43, 7, p. 1699-1710 12 p., 4550646.

Research output: Contribution to journalArticle

77 Scopus citations
2007

Ultra-low power subthreshold current-mode logic utilising PMOS load device

Tajalli, A., Vittoz, E., Leblebici, Y. & Brauer, E. J., Aug 24 2007, In : Electronics Letters. 43, 17, p. 911-913 3 p.

Research output: Contribution to journalArticle

16 Scopus citations

Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept

Tajalli, A., Vittoz, E., Leblebici, Y. & Brauer, E. J., Dec 1 2007, ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference. p. 304-307 4 p. 4430304. (ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

22 Scopus citations
2006

Implementation of structured ASIC fabric using via-programmable differential MCML cells

Badel, S., Hatirnaz, I., Leblebici, Y. & Brauer, E. J., Dec 1 2006, IFIP VLSI-SoIC 2006 - IFIP WG 10.5 International Conference on Very Large Scale Integration and System-on-Chip. p. 234-238 5 p. 4107635. (IFIP VLSI-SoIC 2006 - IFIP WG 10.5 International Conference on Very Large Scale Integration and System-on-Chip).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Via-programmable expanded universal logic gate in MCML for structured ASIC applications: Circuit design

Brauer, E. J., Hatirnaz, I., Badel, S. & Leblebici, Y., Dec 1 2006, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings. p. 2893-2896 4 p. 1693229. (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Via-programmable structured ASIC fabric based on MCML cells: Design flow and implementation

Badel, S., Hatirnaz, I., Leblebici, Y. & Brauer, E. J., Dec 1 2006, Proceedings of the 2006 49th Midwest Symposium on Circuits and Systems, MWSCAS'06. p. 85-88 4 p. 4267078. (Midwest Symposium on Circuits and Systems; vol. 1).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations
2004

Finding efficient inductor geometries in digital CMOS process for RF applications

Brauer, E. J. & Magoon, V., Dec 1 2004, Proceedings of the IASTED International Conference on Circuits, Signals, and Systems. Rashid, M. H. (ed.). p. 558-561 4 p. 449-048. (Proceedings of the IASTED International Conference on Circuits, Signals, and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Low noise MCML prefix adders using 0.18 μm CMOS technology

Brauer, E. J. & Leblebici, Y., Dec 1 2004, Proceedings of the IASTED International Conference on Circuits, Signals, and Systems. Rashid, M. H. (ed.). p. 467-470 4 p. 449-103. (Proceedings of the IASTED International Conference on Circuits, Signals, and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Performance evaluation of CMOS low drop-out voltage regulators

Tantawy, R. & Brauer, E. J., Dec 1 2004, In : Midwest Symposium on Circuits and Systems. 1, p. I141-I144

Research output: Contribution to journalConference article

33 Scopus citations

Sub-70 PS full adder in 0.18 μm CMOS current-mode logic

Brauer, E. J. & Leblebici, Y., Dec 1 2004, Proceedings of the IASTED International Conference on Circuits, Signals, and Systems. Rashid, M. H. (ed.). p. 482-486 5 p. 449-101. (Proceedings of the IASTED International Conference on Circuits, Signals, and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations
2002

Determining the network parameters of the amphibian vision system

Brauer, E. J. & Nishikawa, K., Dec 1 2002, p. I412-I415.

Research output: Contribution to conferencePaper

2001

Real-time interaction between a neuromorphic electronic circuit and the spinal cord

Jung, R., Brauer, E. J. & Abbas, J. J., Sep 27 2001, In : IEEE Transactions on Neural Systems and Rehabilitation Engineering. 9, 3, p. 319-326 8 p.

Research output: Contribution to journalArticle

47 Scopus citations
1999

Analog VLSI-spinal cord interface for motor control

Jung, R., Brauer, E. J., Abbas, J. J. & Grandhe, S., Dec 1 1999, Annual International Conference of the IEEE Engineering in Medicine and Biology - Proceedings. IEEE, 1 p. (Annual International Conference of the IEEE Engineering in Medicine and Biology - Proceedings; vol. 1).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Experimental results of 6 neuron VLSI circuit of lamprey unit pattern generator

Brauer, E. J., Jung, R., Abbas, J. J., Thompsen, B., Hilchie, S. & Tran, A., Dec 1 1999, Annual International Conference of the IEEE Engineering in Medicine and Biology - Proceedings. IEEE, 1 p. (Annual International Conference of the IEEE Engineering in Medicine and Biology - Proceedings; vol. 1).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Graphical user interface for functional neuromuscular stimulation system

Brauer, E. J., Colvin, J. & Abbas, J. J., Dec 1 1999, p. 1105-1108. 4 p.

Research output: Contribution to conferencePaper

Hardware implementation of a neural network pattern shaper algorithm

Brauer, E. J., Abbas, J. J., Callaway, B., Colvin, J. & Farris, J., Dec 1 1999, p. 2315-2318. 4 p.

Research output: Contribution to conferencePaper

1 Scopus citations

Neuromorphic a VLSI circuit of lamprey unit pattern generator

Brauer, E. J., Thompsen, B., Jung, R. & Abbas, J. J., Dec 1 1999, p. 1095-1098. 4 p.

Research output: Contribution to conferencePaper

VLSI circuit of lamprey unit pattern generator

Brauer, E. J., Jung, R., Thompsen, B. & Abbas, J. J., Dec 1 1999, p. 2319-2322. 4 p.

Research output: Contribution to conferencePaper

1998

Additive decomposition applied to the semiconductor drift-diffusion model

Brauer, E. J., Turowski, M. & Mcdonough, J. M., Jan 1 1998, In : VLSI Design. 8, 1-4, p. 393-399 7 p.

Research output: Contribution to journalArticle

Open Access
1997

Analog circuit model of lamprey unit pattern generator

Brauer, E. J., Jung, R., Wilson, D. & Abbas, J. J., Jan 1 1997, In : Proceedings of the IEEE Great Lakes Symposium on VLSI. p. 137-142 6 p.

Research output: Contribution to journalConference article

2 Scopus citations

Full-swing bootstrapped BiCMOS buffer

Brauer, E. J. & Elamanchili, P., Jan 1 1997, In : Proceedings of the IEEE Great Lakes Symposium on VLSI. p. 8-13 6 p.

Research output: Contribution to journalConference article

1 Scopus citations

Sensitivity analysis of an analog circuit model of lamprey unit pattern generator

Brauer, E. J., Jung, R., Wilson, D. & Abbas, J. J., Dec 1 1997, 1997 IEEE International Conference on Neural Networks, ICNN 1997. p. 975-979 5 p. 616158. (IEEE International Conference on Neural Networks - Conference Proceedings; vol. 2).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations
1996

Improved analytic method to calculate emitter follower delay including emitter resistance

Brauer, E. J., Dec 1 1996, p. 309-312. 4 p.

Research output: Contribution to conferencePaper

1995

Estimating node voltages in bipolar circuits using linear programming

Brauer, E. J. & Kang, S. M., Jan 1 1995, In : Proceedings - IEEE International Symposium on Circuits and Systems. 2, p. 901-903 3 p.

Research output: Contribution to journalConference article

1993

Analytic method for calculating current sharing in emitter-coupled bipolar transistors

Brauer, E. J. & Kang, S. M., Dec 1 1993, Midwest Symposium on Circuits and Systems. Publ by IEEE, p. 887-890 4 p. (Midwest Symposium on Circuits and Systems; vol. 2).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Functional verification of ECL circuits including voltage regulators

Brauer, E. J. & Kang, S. M., Jan 1 1993, Proceedings - IEEE International Symposium on Circuits and Systems. Publ by IEEE, p. 1710-1713 4 p. (Proceedings - IEEE International Symposium on Circuits and Systems; vol. 3).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1992

An algorithm for identifying voltage regulators in ECL circuits

Brauer, E. & Hajj, I. N., Jan 1 1992, 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992. Institute of Electrical and Electronics Engineers Inc., p. 2101-2103 3 p. 230579. (Proceedings - IEEE International Symposium on Circuits and Systems; vol. 5).

Research output: Chapter in Book/Report/Conference proceedingConference contribution